Video signal processing apparatus for converting composite image input signals into output signals having increased scan lines

ABSTRACT

A video signal processing apparatus for converting an input analog video signal, including a variable-density image signal and a two-state image signal, into an output analog video signal whose number of scanning lines is increased without degrading the visibility of the two-state image; wherein the input video signal is separated into variable-density image data and two-state image data; then, a portion of the variable-density image data from which the two-state image data is removed, is replaced with a variable-density image data portion immediately before the beginning of the two-state image data; then, the variable-density image data and the two-state image data are stored separately in a memory; then, a general analog-mode enlarge interpolation processing, such as a linear interpolation processing, is performed on the variable-density image data; then, a two-state mode enlarge interpolation processing is performed 10 on the two-state image data; and then, the variable-density image data and the two-state image data, both of which are enlarge interpolated, are recombined.

TECHNICAL FIELD

This invention relates to a video signal processing apparatus forconverting an input analog video signal including a variable-densityimage signal and a two-state image signal into an output analog videosignal with the number of scanning lines increased.

BACKGROUND ART

When displaying an image represented by an input analog video signal bythe use of a cathode ray tube (hereinafter referred to as a CRT) or thelike having a large number of scanning lines in an enlarged orhigh-definition mode, generally, the input video signal is converted byan A-D converter into a digital signal, the digital data correspondingto one frame is stored in a first frame memory, the data held in thisframe memory is converted by an enlarge interpolator into an enlargedimage data signal and written in a second frame memory, and then theimage data held in this second frame memory is successively read out andconverted by a D-A converter into an analog signal, this analog signaloutput being used in displaying the original image in the enlarged orhigh-definition mode. When converting the original image data made up of512×512 pixels into the enlarged image data made up of 1024×1024 pixels,the enlarge interpolator is designed to interpolate, between adjacentoriginal pixels, a new pixel having such an intensity level as tolinearly interpolate the intensity levels of these adjacent originalpixels.

However, if such an interpolation processing is adopted in handling theimage data on which a so-called two-state image is overlaid, forexample, a variable-density image on which another image of character,graphic symbol, cursor, etc. is displayed in superposed form, theinterpolation processing is performed in the surroundings of eachoverlay pixel, or between the overlay pixel having a high intensitylevel and each pixel of the variable-density image generally having alower intensity level than the former; as a result, a new pixel havingan intermediate intensity level between them is interpolated. Therefore,if the thus interpolated enlarged image data is displayed, thesurroundings of the overlay image grow dim, spoiling the sharpness of adisplay of character, graphic symbol, cursor, etc.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a video signalprocessing apparatus for converting an input analog video signalincluding a variable-density image signal and a two-state image signalinto an output video signal with the number of scanning lines increasedwithout spoiling the visibility of a two-state image display.

In brief, the present invention processes an input video signal by;separating the input video signal into variable-density image data andtwo-state image data, replacing a portion of the variable-density imagedata from which the two-state image data is removed with avariable-density image data portion immediately before the beginning ofthe two-state image data, storing the variable-density image data andthe two-state image data separately in memory means, performing ageneral analog-mode enlarge interpolation processing such as a linearinterpolation processing on the variable-density image data, performinga two-state-mode enlarge interpolation processing on the two-state imagedata, and re-combining the variable-density image data and the two-stateimage data both enlarge-interpolated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment of the presentinvention;

FIG. 2 is a diagram showing exemplary input analog video signal andcomposite synchronizing signal;

FIG. 3 is a diagram showing the relationship between the input analogvideo signal, and two-state image data and variable-density image dataseparated from the former;

FIGS. 4A and 4B are diagrams explanatory of an enlarge interpolationprocessing for the variable-density image data; and

FIGS. 5A and 5B are diagrams explanatory of another enlargeinterpolation processing for the two-state image data.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of the present invention will now be described in greaterdetail with reference to the drawings. In FIG. 1, 20 is an A-D converterfor converting an input analog video signal into a digital signal, and21 is a comparator for comparing the level of the input analog videosignal with a threshold voltage internally set to take out only overlaydata whose level exceeds the threshold voltage. This overlay data outputis temporarily held in an overlay data register 22 and sent to an imagedata hold control circuit 23. (The term "circuit" is abbreviated to"CKT" in the drawing.) 24 is an image data register for temporarilyholding the image data converted by the A-D converter 20 into the formof a digital signal, which is controlled by the image data hold controlcircuit 23 either to take in a new data output from the A-D converter 20or to hold the last data. 25 is a pixel clock generating circuit forgenerating a pixel clock signal having a period corresponding to onepixel by multiplying a horizontal synchronizing signal included in aninput composite synchronizing signal by the use of a built-in PLLcircuit or the like. This pixel clock signal generated is sent to theoverlay data register 22, the image data hold control circuit 23, and awrite control circuit 26. This write control circuit 26 generates writeaddress signals in synchronism with the pixel clock signal and appliesthem to a first image data frame memory 27 and a first overlay dataframe memory 28, so that the output data of the image data register 24and the output data of the overlay data register 22 are written in thesememories. 29 is an enlarge interpolator which reads the image data outof the first image data frame memory 27 by sending a read address signalthereto, performs an enlarge interpolation processing, and writes theresult in a second image data frame memory 31. 30 is another enlargeinterpolator which reads the overlay data out of the first overlay dataframe memory 28 by sending a read address signal thereto, performs anenlarge interpolation processing, and writes the result in a secondoverlay data frame memory 32. 33 is a timing signal generating circuitwhich generates a pixel clock signal compatible with the number ofscanning lines increased and applies it to the two enlarge interpolators29 and 30, a synchronizing signal generating circuit 34, and a D-Aconverter 35. This synchronizing signal generating circuit 34 generatesvertical and horizontal synchronizing signals corresponding to thenumber of scanning lines increased in accordance with the pixel clocksignal input to provide a new composite synchronizing signal, and alsogenerates read address signals to be applied to the second image dataframe memory 31 and the second overlay data frame memory 32. The D-Aconverter 35 combines the data read out of the two frame memories 31 and32 into an output analog video signal.

The operation of the foregoing embodiment of the present invention willbe described. The input analog video signal has a waveform correspondingto a variable-density image signal on which an overlay signal issuperposed. FIG. 2 shows such an input analog video signal over onescanning line. As illustrated in FIG. 2, the input analog video signalis composed of a variable-density image signal 50 and an overlay signal51 representing a figure of character, graphic symbol, cursor, etc. 52is a composite synchronizing signal. 53 is a blanking level or referencepotential whose intensity is zero in level. V_(T) is a threshold voltagefor separation of the overlay signal 51 from the variable-density imagesignal 50, which is set to be higher than a potential V_(A)corresponding to the highest intensity level of the variable-densityimage signal 50, but lower than a potential V_(L) corresponding to theintensity level of the overlay signal 51. The input analog video signalis applied to both the A-D converter 20 and the comparator 21. Theanalog video signal applied to the comparator 21 is compared with thethreshold voltage V_(T). Only a signal whose potential is larger thanthe threshold voltage V_(T) is held in the overlay data register 22 asoverlay data and also applied to the image data hold control circuit 23.The write operation into the overlay data register 22 is performed insynchronism with the pixel clock signal from the pixel clock generatingcircuit 25.

The analog video signal applied to the A-D converter 20 is convertedinto a digital signal which is written in the image data register 24 insynchronism with the pixel clock signal from the image data hold controlcircuit 23. However, the supply of the pixel clock signal from the imagedata hold control circuit 23 to the image data register 24 is stoppedwhile the overlay data is being applied to the image data hold controlcircuit 23, i.e. while the output of the comparator 21 is "1";consequently, the write operation of the video signal into the imagedata register 24 is inhibited during the foregoing interval; thus,during the same interval the image data register 24 keeps the dataimmediately before the output of the comparator 21 becomes "1". Suchcircumstances are illustrated in FIG. 3. In FIG. 3, 54 is the "1" outputof the comparator 21 having taken out a signal whose potential exceedsthe threshold voltage V_(T), which is the "overlay data". 55 is thevariable-density image data from which the overlay signal 51 wasremoved. Although the variable-density image data 55 is actually handledin the form of a digital signal, it is illustrated in analog waveformfor convenience of understanding. In the variable-density image data 55,during intervals t1, t2 and t3 corresponding to the signal portionswhere the overlay signal 51 was present, the variable-density image dataof points A, B and C immediately before the output of the comparator 21becomes "1" are preserved, respectively. In this way, the input videosignal is separated into the overlay data 54 and the variable-densityimage data 55 which are written in the overlay data register 22 and theimage data register 24, respectively. The write control circuit 26generates the write address signals pertaining to the first image dataframe memory 27 and the first overlay data frame memory 28 on the basisof the pixel clock signal from the pixel clock generating circuit 25, sothat the data from the image data register 24 and from the overlay dataregister 22 are written in these memories. When the data of one framehas been written in the first image data frame memory 27 and in thefirst overlay data frame memory 28, the enlarge interpolator 29 and theenlarge interpolator 30 read the data out of the first image data framememory 27 and out of the first overlay data frame memory 28, perform therespective enlarge interpolation processings, and write the resultantdata in the second image data frame memory 31 and in the second overlaydata frame memory 32, respectively. At this time, the timing generatingcircuit 33 generates a pixel clock signal compatible with the number ofscanning lines increased and applies it to the enlarge interpolators 29and 30, synchronizing signal generating circuit 34, and D-A converter35. The enlarge interpolators 29 and 30 generate the write addresssignals in synchronism with the pixel clock signal, and write thevariable-density image data and the overlay data both interpolated inthe second image data frame memory 31 and in the second overlay dataframe memory 32, respectively; as a result, an enlarged image is formedby the resultant variable-density data and overlay data.

The interpolation processing is performed as illustrated in FIGS. 4A and4B with respect to the variable-density image data, and as illustratedin FIGS. 5A and 5B with respect to the overlay data. FIG. 4A shows aportion of one frame, made up of 512×512 pixels, for example, of theinput video signal, in which a circle represents a pixel and a numberinside the circle indicates the intensity level of each pixel. FIG. 4Bshows the same portion as that shown in FIG. 4A, that isenlarge-interpolated to a frame made up of 1024×1024 pixels, in which asolid circle corresponds to the original pixel, a dotted circlerepresents an interpolation pixel generated by the enlarge interpolationprocessing, and a number inside the circle indicates the intensity levelof each pixel. The intensity level of the interpolation pixelcorresponds to the mean value in intensity of the original pixelsadjacent to the interpolation pixel. Such interpolation is generallyperformed on the basis of a linear interpolation method. Of course, anyanalog interpolation method can be used. As will be appreciated, sincethe interpolation processing is performed on the variable-density imagedata whose overlay data is removed and replaced with a variable-densityimage data portion immediately before the begining of the overlay data,the interpolation data generated cannot be influenced by the overlaydata. FIG. 5A shows an overlay display portion of one frame made up of512×512 pixels, in which a black circle represents a pixel of highintensity, and a white circle represents a pixel of low (or zero)intensity. FIG. 5B shows the same portion as that shown in FIG. 5A, thatis enlarge-interpolated to a frame made up of 1024×1024 pixels, in whicha black circle corresponds to the original pixel, and a cross-hatchingcircle represents an interpolation pixel generated. This interpolationpixel has the same high intensity as that of the original pixel and isarranged in the same way as the original pixel arrangement. Suchinterpolation is generally performed on the basis of a two-state-imageinterpolation method. Here, since the interpolation processing isperformed on the two-state image data in which no variable-density imagedata is included, the image data generated through interpolation cannotbe influenced by the variable-density image data. That is, thesurroundings of the two-state image cannot grow dim in contrast to theprior art.

The synchronizing signal generating circuit 34 provides the verticalsynchronizing signal and horizontal synchronizing signal for displayingon the CRT in the form of the composite synchronizing signal, andapplies the read address signals to the second image data frame memory31 and the second overlay data frame memory 32, so that the enlargedimage data from these memories are applied to the D-A converter 35. TheD-A converter 35 combines the variable-density image data and theoverlay data and converts the result into an analog signal insynchronism with the pixel clock signal from the timing generatingcircuit 33 to provide an output video signal compatible with the newnumber of scanning lines.

The present invention should not be limited to the foregoing embodiment.That is, although the embodiment enlarges the image by a factor of two,this enlargement factor can be set to any integral number using the samemethod as used in the embodiment. Although the embodiment is describedas using the independent image data frame memories for before and afterinterpolation and the independent overlay data frame memories for beforeand after interpolation, these memories may be replaced with a commonmemory unit which will be put in use by adopting any desired addressmapping system. The image data register 24 may be built in the A-Dconverter 20. Since the overlay data register 22 is used to make thewrite timing of the overlay data into the first overlay data framememory 28 accord with the write timing of the variable-density imagedata into the first image data frame memory 27, it may be omitted if anyadequate timing control system is adopted. The CRT serving as a displayunit for an enlarged image may be replaced with a laser printer, thermalprinter, etc.

While the preferred embodiment has been described, various modificationsand changes may occur to those skilled in the art without departing fromthe spirit and scope of the invention as defined by the appended claims.

What is claimed is:
 1. A video signal processing apparatus forconverting an input analog video signal, whose number of scanning linesis given, including a variable-density image signal and a two-stateimage signal overlaid on the variable-density image signal into anoutput analog video signal whose number of scanning lines is larger thanthat of the input analog video signal, comprisingvariable-density imagesignal extracting means for extracting the variable-density image signalfrom the input analog video signal, a portion of the extractedvariable-density image signal corresponding to the two-state imagesignal being replaced with a variable-density image signal portionimmediately before the beginning of the two-state image signal,two-state image signal extracting means for extracting the two-stateimage signal from the input analog video signal, first memory means forstoring the output signal, corresponding to at least one frame, of thevariable-density image signal extracting means and the output signal,corresponding to at least one frame, of the two-state image signalextracting means in the form of digital image data, variable-densityimage data enlarge-interpolating means for performing an enlargeinterpolation processing on the variable-density image data stored inthe first memory means to generate variable-density image data whosenumber of scanning lines is larger than the corresponding stored image,two-state image data enlarge-interpolating means for performing anenlarge interpolation processing on the two-state image data stored inthe first memory means to generate two-state image data whose number ofscanning lines is larger than the corresponding stored image, secondmemory means for storing the output data, corresponding to at least oneframe, of the variable-density image data enlarge-interpolating meansand the output data, corresponding to at least one frame, of thetwo-state image data enlarge-interpolating means, and analog video dataoutput means for concurrently reading out the variable-density imagedata and the two-state image data stored in the second memory means andcombining these read-out data to provide the output analog video signal.2. A video signal processing apparatus according to claim 1, wherein thetwo-state image signal extracting means is composed of a comparator forcomparing the input analog video signal with a given threshold value andan overlay data register for holding the output signal of the comparatorin the form of two-state data.
 3. A video signal processing apparatusaccording to claim 2, wherein the variable-density image signalextracting means is composed of an A-D converter for converting theinput analog video signal into a digital signal, an image data registerfor holding the output data of the A-D converter, and an image data holdcontrol circuit for inhibiting the data holding of the image dataregister when the two-state output data of the comparator is "1".
 4. Avideo signal processing apparatus according to claim 1, wherein thevariable-density image data enlarge-interpolating means is a linearinterpolator.